// (C) Copyright 2012 Kystar. All rights reserved.

`timescale 1ns/100ps
`default_nettype none

module net_top 
#(parameter
    MAX_VIN_WIDTH = 0,
    FRAME1_START_ADDR = 0,
    AUDIO_EN = 0
)
(
    input  wire          I_sclk,
    input  wire          I_rst_n,
    //
    input  wire          I_new_frame,
    input  wire          I_vib_use_buf1,
    input  wire          I_video_not_active,
    input  wire          I_send_disp_set_pkg_start,
    // rgmii out
    output wire          O_rgmii_txc,
    output wire          O_rgmii_txen,
    output wire [  3: 0] O_rgmii_txd,
    // rgmii in
    input  wire          I_rgmii_rxc,
    input  wire          I_rgmii_rxdv,
    input  wire [  3: 0] I_rgmii_rxd,
    // rgmii check
    output wire          O_px_rxc,
    output wire          O_px_rxdv,
    output wire          O_px_rxer,
    // memory interface
    output wire          O_sdm_vob_req,
    input  wire          I_sdm_vob_ack,
    input  wire          I_sdm_sdram_wr_rd_end,
    output wire          O_sdm_sdram_rd_en,
    output wire [ 31: 0] O_sdm_sdram_start_addr,
    output wire [ 15: 0] O_sdm_sdram_length,
    input  wire [ 31: 0] I_sdm_sdram_rdata,
    input  wire          I_sdm_sdram_rdata_valid,
    // registers
    input  wire [ 11: 0] I_reg_rb_vin_width,
    input  wire          I_reg_px_enable,
    input  wire [ 7: 0]  I_reg_nop_bytes,
    input  wire [ 8: 0]  I_reg_frame_pkg_byte_num,
    input  wire          I_reg_disable_disp_set_pkg,
    input  wire [ 10: 0] I_reg_disp_set_pkg_byte_num,
    input  wire [ 11: 0] I_reg_idle_pkg_byte_num,
    input  wire          I_reg_send_comm_pkg,
    input  wire [ 11: 0] I_reg_comm_pkg_byte_num,
    input  wire [ 10: 0] I_reg_px_start_row,
    input  wire [ 11: 0] I_reg_px_start_col,
    input  wire [ 11: 0] I_reg_px_width,
    input  wire [ 10: 0] I_reg_px_height,
    input  wire          I_reg_clr_comm_back_flag,
    output wire          O_reg_rb_comm_back_flag,
    output wire          O_reg_rb_comm_back_crc_err,
    output wire [ 11: 0] O_reg_rb_comm_back_length,
    output wire          O_reg_rb_sending_comm_pkg,
    input  wire [ 11: 0] I_reg_px_start_row_offset,
    input  wire [ 11: 0] I_reg_px_start_col_offset,
    input  wire          I_reg_mac_addr_incr_en,
    input  wire [ 11: 0] I_reg_max_pixel_num_in_one_trans,
    input  wire          I_reg_long_pkg_en,
    input  wire [ 11: 0] I_reg_px_line_step,
    input  wire          I_reg_px_hori_invert_en,
    input  wire          I_reg_px_vert_invert_en,
    input  wire          I_reg_px_audio_enable,
    // pkg ram interface
    input  wire          I_pkg_ram_wen,
    input  wire [ 11: 0] I_pkg_ram_waddr,
    input  wire [  7: 0] I_pkg_ram_wdata,
    input  wire          I_pkg_ram_rden,
    input  wire [ 11: 0] I_pkg_ram_raddr,
    output reg  [  7: 0] O_pkg_ram_rdata,
    // comm back ram interface
    input  wire          I_comm_back_ram_ren,
    input  wire [ 10: 0] I_comm_back_ram_raddr,
    output reg  [  7: 0] O_comm_back_ram_rdata,
    // audio input
    input  wire          I_audio_data_valid,
    input  wire [  7: 0] I_audio_data,
    //
    output wire          O_reg_reboot_to_test
);

/******************************************************************************
                                <localparams>
******************************************************************************/
localparam
    DISP_DATA_FIFO_DEPTH = 256,
    DISP_DATA_FIFO_DEPTH_BW = log2(DISP_DATA_FIFO_DEPTH);

localparam
    DISP_DATA_FIFO_24B_DEPTH = 256; //1024;

localparam
    FRAME_RAM_DEPTH = 256,
    DISP_SET_RAM_DEPTH = 1024,
    DISP_DATA_RAM_DEPTH = 64,
    IDLE_RAM_DEPTH = 64,
    COMM_RAM_DEPTH = 640,
    COMM_BACK_RAM_DEPTH = 1024;

localparam
    FRAME_RAM_OFFSET = 0,
    DISP_SET_RAM_OFFSET = FRAME_RAM_DEPTH, // 256
    DISP_DATA_RAM_OFFSET = DISP_SET_RAM_OFFSET + DISP_SET_RAM_DEPTH, // 1280
    IDLE_RAM_OFFSET = DISP_DATA_RAM_OFFSET + DISP_DATA_RAM_DEPTH, // 1344
    COMM_RAM_OFFSET = IDLE_RAM_OFFSET + IDLE_RAM_DEPTH; // 1408

localparam
    ORIGINAL_COMM_RAM_OFFSET = 1856; // in docs

localparam
    PKG_RAM_DEPTH = FRAME_RAM_DEPTH + DISP_SET_RAM_DEPTH + DISP_DATA_RAM_DEPTH + IDLE_RAM_DEPTH + COMM_RAM_DEPTH; // 2048

localparam
    AUDIO_FIFO_DEPTH = 10;

/******************************************************************************
                              <internal signals>
******************************************************************************/
reg  new_frame;
reg  [ 11: 0] reg_px_width;
reg  [ 10: 0] reg_px_height;
reg  [ 10: 0] reg_px_start_row;
reg  [ 11: 0] reg_px_start_col;
// frame & disp set
wire req_net_frame;
wire ack_net_frame;
wire net_out_en_frame;
wire [ 7: 0] net_out_data_frame;
wire [ 7: 0] frame_pkg_ram_rdaddr;
wire sending_disp_set_pkg;
wire [ 9: 0] disp_set_pkg_ram_rdaddr;
// disp data
wire req_net_disp_data;
wire ack_net_disp_data;
wire net_out_en_disp_data;
wire [ 7: 0] net_out_data_disp_data;
wire [ 5: 0] disp_data_ram_rdaddr;
// disp data fifo
wire fifo_wrreq;
wire [ 31: 0] fifo_wdata;
wire fifo_empty;
wire fifo_rdreq;
wire [ DISP_DATA_FIFO_DEPTH_BW - 1: 0] fifo_usedw;
wire [ 31: 0] fifo_rddata;
//
wire [ 15: 0] fifo_usedw_24b;
wire fifo_rdreq_24b;
wire [ 23: 0] fifo_rddata_24b;
wire [ 23: 0] fifo_wdata_24b;
wire fifo_wrreq_24b;
// idle pkg
wire req_net_idle;
wire ack_net_idle;
wire net_out_en_idle;
wire [ 7: 0] net_out_data_idle;
wire [ 10: 0] idle_pkg_ram_rdaddr;
// comm send pkg
reg  [ 2: 0] send_comm_pkg_dly;
reg  send_comm_pkg_start;
wire req_net_comm;
wire ack_net_comm;
wire net_out_en_comm;
wire [ 7: 0] net_out_data_comm;
wire [ 10: 0] comm_pkg_ram_rdaddr;
// pkg ram
wire [ 7: 0] pkg_ram_rdata;
reg  [ log2(PKG_RAM_DEPTH) - 1: 0] pkg_ram_rdaddr;
reg           pkg_ram_wen;
reg  [ 11: 0] pkg_ram_waddr;
reg  [  7: 0] pkg_ram_wdata;
wire [  7: 0] pkg_ram_rdata_for_spi_read;
// net rx
wire net_rx_clk;
wire net_in_en;
wire net_in_er;
wire [ 7: 0] net_in_data;
// frame head
reg  [ 11: 0] frame_head_cnt;
reg  disable_idle_pkg;
wire send_idle_pkg_start;
wire send_idle_pkg_ok;
// comm back
wire [ 10: 0] comm_back_ram_waddr;
wire [ 7: 0] comm_back_ram_wdata;
wire comm_back_ram_wrreq;
wire [ 7: 0] comm_back_ram_q;
// audio
wire [ AUDIO_FIFO_DEPTH: 0] audio_fifo_usedw;
wire audio_fifo_rdreq;
wire [ 7: 0] audio_fifo_q;
wire disable_audio_pkg;
wire [ 10: 0] audio_pkg_ram_rdaddr;
wire req_net_audio;
wire ack_net_audio;
wire net_out_en_audio;
wire [ 7: 0] net_out_data_audio;

/******************************************************************************
                                <module body>
******************************************************************************/
//--------------------------------------------------------------------
// frame head
//--------------------------------------------------------------------
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        frame_head_cnt <= 'd0;
    else if (I_new_frame)
        frame_head_cnt <= 12'hfff;
    else if (frame_head_cnt != 'd0)
        frame_head_cnt <= frame_head_cnt - 1'b1;

always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        disable_idle_pkg <= 1'b0;
    else
        disable_idle_pkg <= frame_head_cnt != 'd0;

always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        new_frame <= 1'b0;
    else
        new_frame <= frame_head_cnt == 'd1;

always @(posedge I_sclk)
    if (I_new_frame)
        begin
        if (I_reg_px_width[11:5] == 0)
            reg_px_width <= 'd32;
        //else if (I_reg_px_width >= 4094)
        //    reg_px_width <= 'd4094;
        else
            reg_px_width <= I_reg_px_width;
        end

always @(posedge I_sclk)
    if (I_new_frame)
        begin
        if (I_reg_px_height[10:5] == 0)
            reg_px_height <= 'd32;
        //else if (I_reg_px_width >= 4094)
        //    reg_px_height <= 'd4094;
        else
            reg_px_height <= I_reg_px_height;
        end

always @(posedge I_sclk)
    if (I_new_frame)
        begin
        reg_px_start_row <= I_reg_px_start_row + I_reg_px_start_row_offset;
        reg_px_start_col <= I_reg_px_start_col + I_reg_px_start_col_offset;
        end

//--------------------------------------------------------------------
// pkg ram
//--------------------------------------------------------------------
pkg_ram u_pkg_ram(
    .address_a(pkg_ram_waddr[10:0]),
    .address_b(pkg_ram_rdaddr),
    .clock(I_sclk),
    .data_a(pkg_ram_wdata),
    .data_b(8'd0),
    .wren_a(pkg_ram_wen),
    .wren_b(1'b0),
    .q_a(pkg_ram_rdata_for_spi_read),
    .q_b(pkg_ram_rdata)
);

always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        pkg_ram_wen <= 1'b0;
    else if (I_pkg_ram_wen) begin
        if ((I_pkg_ram_waddr >= COMM_RAM_OFFSET) && (I_pkg_ram_waddr < ORIGINAL_COMM_RAM_OFFSET)) // 1856 is original comm_ram_offset
            pkg_ram_wen <= 1'b0;
        else if (I_pkg_ram_waddr >= ORIGINAL_COMM_RAM_OFFSET + COMM_RAM_DEPTH)
            pkg_ram_wen <= 1'b0;
        else
            pkg_ram_wen <= 1'b1;
    end
    else
        pkg_ram_wen <= 1'b0;

always @(posedge I_sclk)
    if (I_pkg_ram_wen)
        pkg_ram_wdata <= I_pkg_ram_wdata;

always @(posedge I_sclk)
    if (I_pkg_ram_rden)
        O_pkg_ram_rdata <= pkg_ram_rdata_for_spi_read;

//--------------------------------------------------------------------
// net_frame_disp_pkg
//--------------------------------------------------------------------
net_frame_disp_pkg u_net_frame_disp_pkg
(
    .I_sclk(I_sclk),
    .I_rst_n(I_rst_n),
    .I_new_frame(new_frame),
    .I_send_disp_set_pkg_start(I_send_disp_set_pkg_start),
    .O_req_net(req_net_frame),
    .I_ack_net(ack_net_frame),
    .O_net_out_en(net_out_en_frame),
    .O_net_out_data(net_out_data_frame),
    .O_frame_pkg_ram_rdaddr(frame_pkg_ram_rdaddr),
    .I_frame_pkg_ram_rddata(pkg_ram_rdata),
    .O_sending_disp_set_pkg(sending_disp_set_pkg),
    .O_disp_set_pkg_ram_rdaddr(disp_set_pkg_ram_rdaddr),
    .I_disp_set_pkg_ram_rddata(pkg_ram_rdata),
    .I_reg_px_enable(I_reg_px_enable),
    .I_reg_nop_bytes(I_reg_nop_bytes),
    .I_reg_frame_pkg_byte_num(I_reg_frame_pkg_byte_num),
    .I_reg_disable_disp_set_pkg(I_reg_disable_disp_set_pkg),
    .I_reg_disp_set_pkg_byte_num(I_reg_disp_set_pkg_byte_num)
);

//--------------------------------------------------------------------
// net_vob_top
//--------------------------------------------------------------------
net_vob_top
#(
    .MAX_VIN_WIDTH(MAX_VIN_WIDTH),
    .FRAME1_START_ADDR(FRAME1_START_ADDR),
    .DISP_DATA_FIFO_DEPTH(DISP_DATA_FIFO_DEPTH),
    .DISP_DATA_FIFO_DEPTH_BW(DISP_DATA_FIFO_DEPTH_BW)
)
u_net_vob_top
(
    .I_sclk(I_sclk),
    .I_rst_n(I_rst_n),
    .I_new_frame(new_frame),
    .I_vib_use_buf1(I_vib_use_buf1),

    .O_sdm_vob_req(O_sdm_vob_req),
    .I_sdm_vob_ack(I_sdm_vob_ack),
    .I_sdm_sdram_wr_rd_end(I_sdm_sdram_wr_rd_end),
    .O_sdm_sdram_rd_en(O_sdm_sdram_rd_en),
    .O_sdm_sdram_start_addr(O_sdm_sdram_start_addr),
    .O_sdm_sdram_length(O_sdm_sdram_length),
    .I_sdm_sdram_rdata(I_sdm_sdram_rdata),
    .I_sdm_sdram_rdata_valid(I_sdm_sdram_rdata_valid),

    .I_out_fifo_usedw(fifo_usedw),
    .O_out_fifo_wrreq(fifo_wrreq),
    .O_out_fifo_wdata(fifo_wdata),

    .I_reg_rb_vin_width(I_reg_rb_vin_width),
    .I_reg_px_enable(I_reg_px_enable),
    .I_reg_px_start_row(reg_px_start_row),
    .I_reg_px_start_col(reg_px_start_col),
    .I_reg_px_width(reg_px_width),
    .I_reg_px_height(reg_px_height),
    .I_reg_px_line_step(I_reg_px_line_step)
);

// disp data fifo
sync_fifo
#(
    .DWIDTH(32),
    .DEPTH(DISP_DATA_FIFO_DEPTH),
    .SHOW_AHEAD(0)
)
u_disp_data_fifo
(
    .I_sclk(I_sclk),
    .I_rst_n(I_rst_n),
    .I_reset(new_frame),
    .O_full(),
    .I_wrreq(fifo_wrreq),
    .I_data(fifo_wdata),
    .O_empty(fifo_empty),
    .I_rdreq(fifo_rdreq),
    .O_q(fifo_rddata),
    .O_usedw(fifo_usedw)
);

//--------------------------------------------------------------------
// conv_32b_to_24b
//--------------------------------------------------------------------
conv_32b_to_24b
#(
    .OUT_FIFO_DEPTH(DISP_DATA_FIFO_24B_DEPTH)
)
u_conv_32b_to_24b
(
    .I_sclk(I_sclk),
    .I_new_frame(new_frame),
    .I_in_fifo_usedw(fifo_usedw),
    .O_in_fifo_rdreq(fifo_rdreq),
    .I_in_fifo_rddata(fifo_rddata),
    .I_out_fifo_usedw(fifo_usedw_24b),
    .O_out_fifo_wrreq(fifo_wrreq_24b),
    .O_out_fifo_wdata(fifo_wdata_24b)
);

//--------------------------------------------------------------------
// sync_fifo_24b
//--------------------------------------------------------------------
sync_fifo
#(
    .DWIDTH(24),
    .DEPTH(DISP_DATA_FIFO_24B_DEPTH),
    .SHOW_AHEAD(0)
)
u_disp_data_fifo_24b
(
    .I_sclk(I_sclk),
    .I_rst_n(I_rst_n),
    .I_reset(new_frame),
    .O_full(),
    .I_wrreq(fifo_wrreq_24b),
    .I_data(fifo_wdata_24b),
    .O_empty(),
    .I_rdreq(fifo_rdreq_24b),
    .O_q(fifo_rddata_24b),
    .O_usedw(fifo_usedw_24b)
);

//--------------------------------------------------------------------
// net_disp_data_pkg
//--------------------------------------------------------------------
net_disp_data_pkg u_net_disp_data_pkg
(
    .I_sclk(I_sclk),
    .I_rst_n(I_rst_n),
    .I_new_frame(new_frame),
    .I_video_not_active(I_video_not_active),
    .O_req_net(req_net_disp_data),
    .I_ack_net(ack_net_disp_data),
    .O_net_out_en(net_out_en_disp_data),
    .O_net_out_data(net_out_data_disp_data),
    .I_fifo_usedw(fifo_usedw_24b),
    .O_fifo_rdreq(fifo_rdreq_24b),
    .I_fifo_rddata(fifo_rddata_24b),
    .O_disp_data_ram_rdaddr(disp_data_ram_rdaddr),
    .I_disp_data_ram_rddata(pkg_ram_rdata),
    .I_disable_idle_pkg(disable_idle_pkg),
    .O_send_idle_pkg_start(send_idle_pkg_start),
    .I_send_idle_pkg_ok(send_idle_pkg_ok),
    .I_reg_px_enable(I_reg_px_enable),
    .I_reg_px_start_row(reg_px_start_row),
    .I_reg_px_start_col(reg_px_start_col),
    .I_reg_px_width(reg_px_width),
    .I_reg_px_height(reg_px_height),
    .I_reg_mac_addr_incr_en(I_reg_mac_addr_incr_en),
    .I_reg_max_pixel_num_in_one_trans(I_reg_max_pixel_num_in_one_trans),
    .I_reg_long_pkg_en(I_reg_long_pkg_en),
    .I_reg_px_line_step(I_reg_px_line_step)
);

//--------------------------------------------------------------------
// idle pkg
//--------------------------------------------------------------------
net_idle_pkg u_net_idle_pkg
(
    .I_sclk(I_sclk),
    .I_rst_n(I_rst_n),
    .I_sent_pkg_start(send_idle_pkg_start),
    .O_send_pkg_ok(send_idle_pkg_ok),
    .O_sending_pkg(),
    .O_req_net(req_net_idle),
    .I_ack_net(ack_net_idle),
    .O_net_out_en(net_out_en_idle),
    .O_net_out_data(net_out_data_idle),
    .O_pkg_ram_rdaddr(idle_pkg_ram_rdaddr),
    .I_pkg_ram_rddata(pkg_ram_rdata),
    .I_reg_pkg_byte_num(I_reg_idle_pkg_byte_num)
);

always @(posedge I_sclk) begin
    if (I_pkg_ram_wen) begin
    if ((I_pkg_ram_waddr >= ORIGINAL_COMM_RAM_OFFSET) && (I_pkg_ram_waddr < ORIGINAL_COMM_RAM_OFFSET + COMM_RAM_DEPTH))
            pkg_ram_waddr <= I_pkg_ram_waddr - (ORIGINAL_COMM_RAM_OFFSET - COMM_RAM_OFFSET);
        else
            pkg_ram_waddr <= I_pkg_ram_waddr;
    end
    else begin
    if ((I_pkg_ram_raddr >= ORIGINAL_COMM_RAM_OFFSET) && (I_pkg_ram_raddr < ORIGINAL_COMM_RAM_OFFSET + COMM_RAM_DEPTH))
            pkg_ram_waddr <= I_pkg_ram_raddr - (ORIGINAL_COMM_RAM_OFFSET - COMM_RAM_OFFSET);
        else
            pkg_ram_waddr <= I_pkg_ram_raddr;
    end
end

always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        pkg_ram_rdaddr <= 'd0;
    else if (ack_net_frame)
        begin
        if (sending_disp_set_pkg)
            pkg_ram_rdaddr <= DISP_SET_RAM_OFFSET + disp_set_pkg_ram_rdaddr;
        else
            pkg_ram_rdaddr <= FRAME_RAM_OFFSET + frame_pkg_ram_rdaddr;
        end
    else if (ack_net_disp_data)
        pkg_ram_rdaddr <= DISP_DATA_RAM_OFFSET + disp_data_ram_rdaddr;
    else if (ack_net_idle)
        pkg_ram_rdaddr <= IDLE_RAM_OFFSET + idle_pkg_ram_rdaddr;
    else if (ack_net_comm)
        pkg_ram_rdaddr <= COMM_RAM_OFFSET + comm_pkg_ram_rdaddr;
    else if (ack_net_audio)
        pkg_ram_rdaddr <= IDLE_RAM_OFFSET + audio_pkg_ram_rdaddr;

//--------------------------------------------------------------------
// comm pkg
//--------------------------------------------------------------------
net_comm_idle_pkg u_net_comm_pkg
(
    .I_sclk(I_sclk),
    .I_rst_n(I_rst_n),
    .I_sent_pkg_start(send_comm_pkg_start),
    .O_send_pkg_ok(),
    .O_sending_pkg(O_reg_rb_sending_comm_pkg),
    .O_req_net(req_net_comm),
    .I_ack_net(ack_net_comm),
    .O_net_out_en(net_out_en_comm),
    .O_net_out_data(net_out_data_comm),
    .O_pkg_ram_rdaddr(comm_pkg_ram_rdaddr),
    .I_pkg_ram_rddata(pkg_ram_rdata),
    .I_reg_pkg_byte_num(I_reg_comm_pkg_byte_num)
);

always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        send_comm_pkg_dly <= 1'b0;
    else
        send_comm_pkg_dly <= {send_comm_pkg_dly[1:0],I_reg_send_comm_pkg};

always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        send_comm_pkg_start <= 1'b0;
    else 
        send_comm_pkg_start <= !send_comm_pkg_dly[2] && send_comm_pkg_dly[1];

//--------------------------------------------------------------------
// net_comm_back_pkg
//--------------------------------------------------------------------
net_comm_back_pkg u_net_comm_back_pkg
(
    .I_sclk(I_sclk),
    .I_rst_n(I_rst_n),
    .I_net_rx_clk(net_rx_clk),
    .I_net_in_en(net_in_en),
    .I_net_in_data(net_in_data),
    .O_comm_back_ram_waddr(comm_back_ram_waddr),
    .O_comm_back_ram_wdata(comm_back_ram_wdata),
    .O_comm_back_ram_wrreq(comm_back_ram_wrreq),
    .I_reg_clr_comm_back_flag(I_reg_clr_comm_back_flag),
    .O_reg_rb_comm_back_flag(O_reg_rb_comm_back_flag),
    .O_reg_rb_comm_back_crc_err(O_reg_rb_comm_back_crc_err),
    .O_reg_rb_comm_back_length(O_reg_rb_comm_back_length),
    .O_reg_reboot_to_test(O_reg_reboot_to_test)
);

// comm back ram
dpram1024x8 u_dpram1024x8(
    .data(comm_back_ram_wdata),
    .rdaddress(I_comm_back_ram_raddr[9:0]),
    .rdclock(I_sclk),
    .wraddress(comm_back_ram_waddr[9:0]),
    .wrclock(net_rx_clk),
    .wren(comm_back_ram_wrreq),
    .q(comm_back_ram_q)
);

always @(posedge I_sclk)
    if (I_comm_back_ram_ren)
        O_comm_back_ram_rdata <= comm_back_ram_q;

//--------------------------------------------------------------------
// net arbitration
//--------------------------------------------------------------------
net_arbi u_net_arbi
(
    .I_sclk(I_sclk),
    .I_rst_n(I_rst_n),
    .I_req_net_0(req_net_frame),
    .O_ack_net_0(ack_net_frame),
    .I_req_net_1(req_net_audio),
    .O_ack_net_1(ack_net_audio),
    .I_req_net_2(req_net_disp_data),
    .O_ack_net_2(ack_net_disp_data),
    .I_req_net_3(req_net_comm),
    .O_ack_net_3(ack_net_comm),
    .I_req_net_4(req_net_idle),
    .O_ack_net_4(ack_net_idle),
    .I_reg_nop_bytes(I_reg_nop_bytes)
);

//--------------------------------------------------------------------
// net output
//--------------------------------------------------------------------
net_output u_net_output
(
    .I_sclk(I_sclk),
    .I_rst_n(I_rst_n),
    .I_ack_net_frame(ack_net_frame),
    .I_net_out_en_frame(net_out_en_frame),
    .I_net_out_data_frame(net_out_data_frame),
    .I_ack_net_disp_data(ack_net_disp_data),
    .I_net_out_en_disp_data(net_out_en_disp_data),
    .I_net_out_data_disp_data(net_out_data_disp_data),
    .I_ack_net_idle(ack_net_idle),
    .I_net_out_en_idle(net_out_en_idle),
    .I_net_out_data_idle(net_out_data_idle),
    .I_ack_net_comm(ack_net_comm),
    .I_net_out_en_comm(net_out_en_comm),
    .I_net_out_data_comm(net_out_data_comm),
    .I_ack_net_audio(ack_net_audio),
    .I_net_out_en_audio(net_out_en_audio),
    .I_net_out_data_audio(net_out_data_audio),
    .I_reg_mac_addr_incr_en(I_reg_mac_addr_incr_en),
    .O_rgmii_txc(O_rgmii_txc),
    .O_rgmii_txen(O_rgmii_txen),
    .O_rgmii_txd(O_rgmii_txd)
);

//--------------------------------------------------------------------
// net input
//--------------------------------------------------------------------
iddr_ctr u_iddr_ctr
(
    .I_rgmii_px_rxc(I_rgmii_rxc),
    .I_rgmii_px_rxdv(I_rgmii_rxdv),
    .I_rgmii_px_rxd(I_rgmii_rxd),

    .O_px_rxc(net_rx_clk),
    .O_px_rxdv(net_in_en),
    .O_px_rxer(net_in_er),
    .O_px_rxd(net_in_data)
);

assign O_px_rxc  = net_rx_clk;
assign O_px_rxdv = net_in_en;
assign O_px_rxer = net_in_er;

//--------------------------------------------------------------------
// audio
//--------------------------------------------------------------------
generate if (AUDIO_EN == 1) begin
sync_fifo
#(
    .DWIDTH(8),
    .DEPTH(1<<AUDIO_FIFO_DEPTH),
    .SHOW_AHEAD(0)
)
u_sync_fifo_audio
(
    .I_sclk(I_sclk),
    .I_rst_n(I_rst_n),
    .I_reset(1'b0),
    .O_full(),
    .I_wrreq(I_audio_data_valid),
    .I_data(I_audio_data),
    .O_empty(),
    .I_rdreq(audio_fifo_rdreq),
    .O_q(audio_fifo_q),
    .O_usedw(audio_fifo_usedw)
);

assign disable_audio_pkg = disable_idle_pkg;

net_audio_pkg
#(
    .AUDIO_FIFO_DEPTH(AUDIO_FIFO_DEPTH)
)
u_net_audio_pkg
(
    .I_sclk(I_sclk),
    .I_rst_n(I_rst_n),
    .O_req_net(req_net_audio),
    .I_ack_net(ack_net_audio),
    .O_net_out_en(net_out_en_audio),
    .O_net_out_data(net_out_data_audio),
    .I_audio_fifo_usedw(audio_fifo_usedw),
    .O_audio_fifo_rdreq(audio_fifo_rdreq),
    .I_audio_fifo_q(audio_fifo_q),
    .I_disable_audio_pkg(disable_audio_pkg),
    .O_pkg_ram_rdaddr(audio_pkg_ram_rdaddr),
    .I_pkg_ram_rddata(pkg_ram_rdata),
    .I_reg_audio_enable(I_reg_px_audio_enable)
);

end
endgenerate

//--------------------------------------------------------------------
// functions
//--------------------------------------------------------------------
function integer log2;
    input  [ 31: 0] value;
    begin
    for (log2 = 0; value > 0; log2 = log2 + 1)
        value = value >> 1;
    end
endfunction

endmodule
`default_nettype wire

